1. Field of the Invention
The present invention relates to a multilayered chip capacitor, and more particularly to a multilayered chip capacitor having a low equivalent series inductance (ESL), which is properly used as a decoupling capacitor in a high frequency circuit.
2. Description of the Related Art
Generally, a multilayered chip capacitor (MLCC) has a structure such that internal electrodes are inserted between a plurality of dielectric layers. Such a multilayered chip capacitor has a small size and a high capacity, and is easily mounted, thus being widely used as a component of various electronic devices. Particularly, the multilayered chip capacitor serves as a decoupling capacitor, which is electrically connected between a semiconductor chip and a power source in a power circuit, such as an LSI.
In order to suppress sudden variation in current and stabilize the power circuit, the multilayered chip capacitor, serving as the decoupling capacitor, requires a low equivalent series inductance (ESL). The above requirement is increased so as to satisfy high-frequency and high-current trends of recent electronic devices.
In order to lower the ESL, there was proposed a method employing a novel arrangement of leads, which is disclosed by U.S. Pat. No. 5,880,925. FIGS. 1a and 1b illustrate a multilayered chip capacitor, in which leads of first and second internal electrodes having different polarities are alternately arranged.
With reference to FIG. 1a, internal electrodes 12 and 13 are respectively formed on a plurality of dielectric layers 11a to 11h. The internal electrodes are divided into first internal electrodes 12 and second internal electrodes 13, and two leads 14 and 15 are formed on each of opposite two sides of the first and second internal electrodes 12 and 13. The dielectric layers 11a to 11h including the first and second internal electrodes 12 and 13 as shown in FIG. 1a are laminated to form a capacitor main body 11, and external terminals 16 and 17 connected to the leads 14 and 15 are formed on the capacitor main body 11, thereby producing a multilayered chip capacitor 10 as shown in FIG. 1b. 
Here, since the leads 14 of the first internal electrodes 12 alternate with the leads 15 of the second internal electrodes 13, the directions of current flowing along the neighboring internal electrodes 12 and 13 are opposite to each other. Parasitic inductance generated from one of the first and second internal electrodes 12 and 13 is partially offset against parasitic inductance generated from the neighboring the other one of the first and second internal electrodes 12 and 13, thereby achieving low ESL characteristics.
However, the above-described multilayered chip capacitor cannot have sufficient ESL reduction effects. That is, since the leads 14 and 15 are alternately disposed, parts of the inductances are opposite to each other. Further, since inner areas of the first and second internal electrodes 12 and 13, which are not close to the leads 14 and 15, do not have a constant flow of current, but have a random flow of current, it is difficult to offset a large quantity of the inductances.
In view of the above problems, there was proposed a method for deforming shapes of internal electrodes. Japanese Patent Laid-open No. 2002-164256 discloses structures of internal electrodes as shown in FIG. 2. FIG. 2 illustrates first and second internal electrodes 22 and 23 connected to different polarities.
Two dielectric layers 21a and 21b as shown in FIG. 2 are laminated to form a part of a capacitor main body. The first internal electrode 22, in which current flows in a clockwise direction, is formed on one dielectric layer 21a, and the second internal electrode 23, in which current flows in a counterclockwise direction, is formed on the other dielectric layer 21b. Here, the first and second internal electrodes 22 and 23 have opposite directions of current, thereby reducing ESL.
However, since the leads 24 and 25 are disposed at different positions in the above method for deforming the structures of the internal electrodes, the first and second internal electrodes 22 and 23 have different shapes. Accordingly, it is difficult to properly design internal electrodes of a multilayered chip capacitor based on desirable characteristics of the capacitor. Further, the first and second internal electrodes 22 and 23, which have complicated linear shapes, increase difference of inductance characteristics due to mismatching of the first and second internal electrodes 22 and 23 in a laminating process.